Resume of Paul
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Overview:

Innovative and hardworking verification engineer with seven years of experience, interested in working on verification, validation, or design, for challenging projects using the most recent technology and tools. Always open to new areas of work and study.

Summary of Qualifications:

  • Verification, validation, integration, design, and documentation of digital circuits in custom processor ASIC’s, MIPS SOC’s, ATM, Sonet, Ethernet, and control ASIC’s using knowledge of e, Specman, VHDL, Verilog, FIFO’s, TCL, Scan, FPGA’s, PID Controllers, Digital filters, and Software to Hardware interface programming

  • Use of CAD tools such as Synopsys Vera and VCS, Verisity Specman, Cadence nc suite, signalscan, virsim, Debussy, Source III VTRAN, Synopsys formality, dc_shell, primetime, and Xilinx Foundation

  •  Programming Languages – Vera, e, VERILOG, VHDL, TCL, C, MIPS Assembly

  • Use of electronic analysis tools and testers for bringing up devices in a lab environment

  • Reliable, efficient and accurate; dedicated to quality results

  • Work well with people of various backgrounds and ideas

Work Experience:

Vihana, Inc., Sunnyvale, CA                                                    12/18/2003 – Present

Senior Member Technical Staff, ASIC Verification –

  • Sole responsibility for block and system level verification of a proprietary DMA engine running over a PCI/PCI-X interface. Completing the entire testplan development and successfully executing it before tapeout was a key contribution to enabling a bug-free DMA engine in 1st silicon. Developed the testplan, coverage goals, and schedule. Coded the entire self-checking and directed/random DMA testbench and PCI/PCI-X BFM interfaces as well as the PCI/PCI-X coverage scenarios. Implemented a complex muti-scenario DMA memory management routine also used by the entire chip-level testbench. Achieved 100% functional and line coverage with the directed/random test enviornment. Also responsible for testing the entire DMA and PCI/PCI-X error handling and recovery procedures, including interrupt servicing. Documentation of DMA testbench and error handling procedures.

  • Responsible for the post-silicon compliance of the PCI/PCI-X 133 MHz interface to both the PCI specification revision 2.3 and PCI-X specification revision 1.0b. Selection of VMETRO hardware tools, creation of testplan and schedule, and execution of all tests. Use of both VMETRO’s Vanguard PCI/PCI-X bus analyzer/exerciser and RTL testbench to test every PCI-SIG compliance checklist item. Coverage achieved in both PCI and PCI-X bus modes. Documentation of testplan and testbench. 

  • Participated in gatelevel verification of JTAG and IBM Memory Array BIST over JTAG.

  •  Responsible for testplan creation and documentation of the Vihana run-time software based error detection, handling, and recovery of hardware errors.

PMC-Sierra, Inc., Santa Clara, CA                                      8/16/1999 – 12/16/2003

Product Design Engineer, Micro-Processor & Optical Networking Divisions –

  • Block and system level verification using Specman and e. Completed verification of a MIPS SOC’s DMA Gigabit Etherent to Memory block. Specifically completed the interrupt based packet processing engine, descriptor and buffer management, and protocol error cases, as well as test case, test plan, and revision control management. Similar experience with designing and implementing a Specman and Verilog simulation environment for a MIPS CPU core with a proprietary transaction based interface.

  • Chip level validation of an ATM traffic manager using a Compact-PCI station and TCL environment. Specifically tested against the ATM standard for Fault Monitroing and Change of State FIFO Operation. TCL test programs were self-checking and interfaced to the PCI station, Windows, and an Adtech traffic generator. The PCI station also contained FPGA traffic generation boards for multi-phy and other traffic scenarios.

  • Top Level Device Integration, including netlist generation, scripting, and interfacing with Layout and Product Engineering for Scan Vectors. Top level work included Integration, JTAG, Scan, and revision control of a 1.5 million gate, 64-Mbit Embedded DRAM, OC-48 ATM traffic manager chip that was a Rev. A success. Also, completed JTAG, Scan, and revision control of a 2 million gate Gigabit Ethernet over Sonet transport chip.

  • Use of VHDL and Synopsys for design and synthesis, as well as Mentor Fast Scan Insertion and ATPG for the DFT flow. Specifically completing all the above tasks of a 12K gate UL2 to UL3 FIFO based converter running at 52 MHz UL2 side and 125 MHz UL3 side. Added TUG-3 SDH support to an existing 20K gate Sonet Transmit VC block.

IBM, San Jose, CA                                                                 6/29/1998 – 8/16/1999

Development Engineer for Test Engineering, Storage Systems Division –

  • Completed the design, production, debug, and documentation of a multi-speed motor control circuit board that reduced tester cost and improved motor control. Use of Xilinx Foundation software, FPGA’s, and VHDL as design tools.

  •  Maintained, upgraded, and documented the hardware control software for a manufacturing line tester using C++ and a proprietary command interpreter as programming tools. Manufacturing line and clean room experience.

  • Created and maintained a department Website running on Windows NT Workstation using IIS 4.0, perl for NT, MS Front Page, and MS Office.

Education:

University of California, Davis, CA. Bachelor of Science, Electrical Engineering; Graduated June 19, 1998 with Highest Honors.